1. Field of the Invention
The invention relates in general to a phase detector, and more particularly to a phase detector applied in a phase-lock loop clock recovery system.
2. Description of the Related Art
For ordinary synchronous transmission of digital signal, data signal is transmitted to a receiving unit in a fixed rate of transmission by a transmitting unit. Normally, the receiving unit uses a phase-lock loop clock recovery system to detect the phase difference between the received data signal and the clock signal of the receiving unit and demodulate the phase and frequency of the clock signal of the receiving unit. Thus, the clock signal of the receiving unit will have same phase and frequency with the received data signal, facilitating the receiving unit to perform sampling and demodulation on the data signal.
Referring to FIG. 1, a block diagram of a conventional phase-lock loop clock recovery system is shown. Conventional phase-lock loop clock recovery system 100 comprises a phase detector 102, a charge pump 104, a loop filter 106 and a voltage controlled oscillator (VCO) 108. The phase detector 102 is for detecting the phase difference between a data signal DT and a clock signal CLK, and outputting a first up signal UP1, a first down signal DN2 and a second down signal DN3 and a second up signal UP4 to charge pump 104 correspondingly. The charge pump 104 correspondingly outputs a phase error signal PE to the loop filter 106, wherein the phase error signal PE corresponds to the phase difference between the data signal DT and the clock signal CLK. The loop filter 106 low-pass filters the phase error signal PE and generates an output signal LFO. The VCO 108 demodulates the frequency and phase of the outputted clock signal CLK according to the voltage level of signal LFO, so that the clock signal CLK can have the same phase and frequency with that of the data signal DT. Of which, when the first up signal UP1 or the second up signal UP4 is enabled, the voltage of the phase error signal PE will rise up; when the first down signal DN2 or the second down signal DN3 is enabled, the voltage of the phase error signal PE will fall down.
Referring to FIG. 2, a detailed circuit diagram of a conventional phase detector 102a is shown. The phase detector 102 comprises a first D-type latch 202, a second D-type latch 204, a third D-type latch 206, a fourth D-type latch 208, a fifth D-type latch 210, a first Exclusive-OR gate (XOR gate) 212, a second XOR gate 214, a third XOR gate 216 and a fourth XOR gate 218.
The input end D1 of the first D-type latch 202 is for receiving the data signal DT. When the clock signal CLK is at a low level, the data signal DT is transmitted to the output end Q1 of the first D-type latch 202. The input end D2 of the second D-type latch 204 is for receiving the output signal of the first D-type latch 202. When the clock signal CLK is at a high level, the output signal of the first D-type latch 202 is transmitted to the output end Q2 of the second D-type latch 204. The input end D3 of the third D-type latch 206 is for receiving the output signal of the second D-type latch 204. When the clock signal CLK is at a low level, the output signal of the second D-type latch 204 is transmitted to the output end Q3 of the third D-type latch 206. The input end D4 of the fourth D-type latch 208 is for receiving the output signal of the third D-type latch 206. When the clock signal CLK is at a high level, the output signal of the third D-type latch 206 is transmitted to the output end Q4 of the fourth D-type latch 208. The input end D5 of the fifth D-type latch 210 is for receiving the output signal of the D-type latch 208. When the clock signal CLK is at a high level, the output signal of the fourth D-type latch 208 is transmitted to the output end Q5 of the fifth D-type latch 210.
The first XOR gate 212 generates a first up signal UP1 according to the data signal DT and the output signal of the second D-type latch 204. The second XOR gate 214 generates a first down signal DN2 according to the output signal of the second D-type latch 204 and the output signal of the third D-type latch 206. The third XOR gate 216 generates a second down signal DN3 according to the output signal of the third D-type latch 206 and the output signal of the fourth D-type latch 208. The fourth XOR gate 218 generates a second up signal UP4 according to the output signal of the fourth D-type latch 208 and the output signal of the fifth D-type latch 210.
Referring to FIG. 3, a signal wave pattern of the phase detector 102a in FIG. 2 is shown. Let the enabling signal be a high level signal. The front edge of the first up signal UP1 will vary with the front edge or the rear edge of the data signal DT. When the front edge of or the rear edge of the data signal DT is ahead of the rising edge or the falling edge of the clock signal CLK, the average value of the phase error signal PE outputted by the charge pump 104 will rise up, so as to increase the frequency and fasten the phase of the clock signal outputted by VCO 108. To the contrary, when the front edge of or the rear edge of the data signal DT is behind the rising edge or the falling edge of the clock signal CLK, the average value of the phase error signal PE outputted by the charge pump 104 will fall down, so as to reduce the frequency of and lower the phase of the clock signal outputted by the VCO 108.
The pulse width of the first up signal UP1 of the conventional the phase detector 102 is between 0 to 1 period of the clock signal CLK, while the pulse width of the first down signal DN2, the second down signal DN3, and the second up signal UP4 is only 1/2 of the period of the clock signal CLK. When the data signal DT is close to be 1/2 period behind the clock signal CLK behind the clock signal CLK, the phase detector 102 is more likely to misinterpret that the data signal DT is ahead of the clock signal CLK and generate a large quantity of the pluses of the first up signal UP1 to fasten the phase of the clock signal CLK and increase the frequency of the clock signal CLK. Consequently, the phase-lock loop clock recovery system 100 may not be locked or may take a longer time to be locked. This situation is more likely to occur during the initial status. Therefore, the phase locking range of the conventional phase-lock loop clock recovery system 100 is limited to when the phase difference is between 180° to −180°.
Besides, when the level transition of the data signal DT concurs with the rising edge of the clock signal CLK, the conventional phase detector 102 might have unlock problem due to the divergence of the phase error signal PE. Referring to FIG. 4, a signal wave pattern of the phase detector 102a when the level transition of the data signal DT concurs with the rising edge of the clock signal CLK is shown. Under this circumstance of concurrence, the first XOR gate 212 might misinterpret the situation and make the first up signal UP1 generate pulses continuously. By doing so, the phase error signal PE will continue to rise up and diverge, preventing the conventional phase-lock loop clock recovery system 100 from being locked or resulting in a much longer locking time.
Apart from the above-mentioned problems, the conventional phase-lock loop clock recovery system 100 might change its precision level and cause errors due to the occurrence of jitters or noises. Referring to FIG. 5, another wave pattern of the conventional phase detector is shown. Given that the width of a pulse 502 of the data signal DT is smaller than the period of a clock signal CLK and that the rising edge of the pulse occurs when the clock signal CLK is at a high level, only the first up signal UP1 will correspondingly generate a pulse 504, but the first down signal DN2, the second down signal DN3 and the second up signal UP4 will not. Consequently, the direct current level of the phase error signal PE might be boosted further, which might cause unlock problem to the phase-lock loop clock recovery system 100 due to the divergence of the phase error signal PE.
Referring to FIG. 6, a third wave pattern of the conventional phase detector 102a is shown. Given that the falling edge 602A of a pulse 602 of the data signal DT occurs when the clock signal CLK is at a high level, that the distance between the rising edge of 604A of next pulse 604 of the data signal DT and the falling edge 602A is smaller than 1/2 period of the clock signal CLK, and that the rising edge 604A occurs when the clock signal CLK is at a low level, likewise, only the first up signal UP1 will correspondingly generate a pulse 606, but the first down signal DN2, the second down signal DN3 and the second up signal UP4 will not. Consequently, the direct current level of the phase error signal PE might be boosted further, which might cause unlock problem to the phase-lock loop clock recovery system 100 due to the divergence of the phase error signal PE.